SMBus Communication Program 1.02 (C) 2001 by Martin Rehak; rayer^seznam*cz
Designed for 82731 (PIIX4) motherboards only!
compiled by GCC 2.95.3 at 12:46, 11.8.2001

intel 82731 south bridge detected as PCI#0 device 7 h
Vedndor ID: 8086 h
Device ID: 7113 h
SMBus revision ID: 0 h
SMBus base address: 5000 h
Please wait, loading DIMM 1 SPD EEPROM data...
DIMM SPD EEPROM Size:                   256 Bytes, used 128 Bytes
DIMM SPD revision/checksum:             0.2 / 8D h - O.K.
Memory Type:                            SD-RAM
Memory Rows/Columns Address Bits:       12 / 9
Module Rows:                            2
Module Data Width:                      64
Module Interface Signal Levels:         LVTTL
Module ECC/EDC mode:                    None
SD-RAM Width/ECC Width:                 8 / 0
SD-RAM Banks:                           4
SD-RAM Cycle/Access Time (1st Hi. CAS): 7.5 ns / 5.4 ns
SD-RAM Cycle/Access Time (2nd Hi. CAS): 0.0 ns / 0.0 ns
SD-RAM Cycle/Access Time (3rd Hi. CAS): 0.0 ns / 0.0 ns
Minimum Row Precharge Time:             20 ns
Minimum Row Active to Row Active Delay: 15 ns
Minimum RAS to CAS Delay:               20 ns
Minimum RAS Pulse Width:                45 ns
Refresh Period:                         Self Refresh, Normal (15.625 ęs)
Burst Length Page supported:            1, 2, 4, 8
Density of Each Row/Total:              2 x 64 MB / 128 MB
Intel Specification Frequency:          133 MHz (estimated)
Manufacturer (via JEDEC IDCode 400000): MOSEL Vitelic - www.moselvitelic.com
Assembly Serial Number:                 0